Aldec Delivers a Dynamic Reconfigurable FPGA Design Flow ManagerFlow Manager Lets Designers Utilize Any Synthesis and Implementation Tools from a Single Environment
Contact:
Megan Moran
Aldec, Inc.
(702) 990-4400 ext. 201
meganm@aldec.com
Henderson Nevada, October 30th, 2001 -- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), announced today that Active-HDL now offers a fully customizable and flexible Design Flow Manager that interfaces with all leading industry-based FPGA synthesis and implementation products. Design teams and IT departments no longer need to learn and maintain multiple product configurations on the network. Active-HDL has completely automated the design process with its reconfigurable Design Flow Manager, which maintains all design files, reports and the status of the designs in one common location.
Advantages of On-the-Fly Reconfiguration
The new Design Flow Manager now supports designs regardless of vendor tools or FPGA architecture. This independence is of most benefit to system designers because third party EDA tools can all be invoked from a single location and designers can have one common graphical user interface (GUI) for all designs. The dynamic nature of the flow allows system designers to control synthesis and implementation from the Active-HDL environment. All FPGA vendor-supplied synthesis and implementation tools are supported, and design teams can freely switch between Altera, Cypress, Xilinx and other vendor tools. Highly specialized design teams within a larger corporation can use the same Active-HDL software for all FPGA applications.
IT and Management Control
Active-HDL's new Design Flow Manager simplifies the network configuration process for IT departments because the end user's machine can be customized to support only those licenses and systems that are available to that specific PC. This licensing customization feature prevents restricted licenses of synthesis and implementation tools to be mistakenly called upon during the design process.
The flow was made to provide maximum flexibility for the entire design process. It enables designers to disable certain parts of the design flow so that they can concentrate on the specific areas of the design cycle that they are currently working on. The flow also permits designers to edit the list of tools supported so that only those that a designer uses most frequently will be invoked.
Project Control
When synthesis and implementation are run in batch mode, the FPGA Design Flow Manager back-annotates the results directly into the Active-HDL environment so that system designers do not have to manually transfer the results. This allows tracking the design progress from one centralized location. Since all files are managed through a single project manager, the users are able to quickly run gate level and timing simulations with the same stimuli files.
Easy To Use and Customize
With the Tcl-based flows, designers can customize the flows and add additional tools that may be required during the verification process, adding flexibility to the design process. Because Active-HDL allows instant addition of user-approved tools, this improves his or her confidence in the design results.
Availability
Active-HDL's dynamic Design Flow Manager is now available as part of the Active-HDL design entry and verification environment. The product includes Aldec's HDL Project Manager, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.
About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.
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